EDA News H' Monday March 31, 2003 From: EDAToolsCafe _____ CareersCafe.com _____ About This Issue H' ASICs versus FPGAs Hedging your bets in a fluid market _____ March 24-28, 2003 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ Far and away the best part of being a journalist is having the opportunity to talk to a range of people about a diverse set of topics. This week is no different as three very likable individuals were willing to take time from their busy schedules to explain their perspectives on the current state of affairs in the ASIC versus FPGA controversy - and whether or not there's a controversy there at all. Bob Payne, U.S. CTO and Senior Vice President/General Manager of System ASIC Technology at Philips Semiconductors, gave one of the keynotes last Tuesday morning, March 25th, at the IEEE International Symposium on Quality Electronic Design (ISQED) in Santa Clara, CA. I talked with Payne later in the day and he said, although there were not as many in attendance at the conference as one might have wished for - many would-be attendees appeared to have canceled travel plans in the first few days of the war - that his talk and those of his fellow keynoters, Toshiba's Susumu Kohyama and Cadence's Ted Vucurevich, were well received. He said both Kohyama and Vucurevich appeared to agree, in the main, with his argument that platform-based design has come of age. Payne said that the flexibility offered by the platform design paradigm offers customers everything they need at this point for speedy and reliable product design and differentiation and, hence, eliminates any need to move to an FPGA-based strategy to achieve design cost and scheduling efficiency. Payne's a relaxed fellow and a fine spokesman for the Philips point of view. He's also, by his own description, an ASIC guy who goes back 30 years in the industry: "I did my first CMOS in 1972." It's probably safe to say that what Bob Payne doesn't know about the ASIC landscape, isn't worth knowing. And Payne is quite clear - neither Philips nor any of the other large ASIC vendors see any threat from an emerging FPGA market. "We're not feeling at all threatened by any of the FPGA guys. They're generally going after the low-volume customers. The FPGA guys might have thousands of customers, with utilization in the thousands or tens of thousands of units. But the SoC guys are in a narrow range of market-share leaders. They're typically building in the million units and beyond region." Meanwhile, Payne is equally clear in commending the role that FPGAs play in the prototyping of designs, a role they've played for a long time. "I've always used the expression, 'FPGAs are god's gift to prototyping and you need to use the gift.' I love FPGAs for full-speed, real-time prototyping. Philips' strategy is to build platforms with extensibility. We create IP down on the FPGAs. Then we have it appear as if it's communicating on the busses of the platform on the 'South' chip - which is the FPGA - and actually talking to the structures of the 'North' chip to provide streaming functions, and new peripherals, and so forth." "Because we're running at full speed, in real time, we can have the complete software environment on the hardware platform. We get the benefits of an FPGA, but with the performance and density benefits of an ASIC. Philips has adopted a derivative-design friendly approach. So you can prototype, you can use the platform, you can do the whole thing - adding new pieces with functionality, which you can validate with an FPGA. Then you put the cell into high-volume consumer applications with a 100% performance chip. We want to provide our customers with the ability to get new functionality completely validated at full speed, in real time. I'm happy with what's going on in the FPGA because it provides that ability." Philips partners with Xilinx and Altera, and Payne says he respects the work of the FPGA vendors: "We view our relationship with Xilinx and Altera as good relationships. We utilize their parts and have a very harmonious relationship, but we don't view ourselves in competition with them. We're on a completely different playing field from the FPGA guys." You'll get a completely different point of view if you have a chance to discuss the ASIC-versus-FPGA thing with Jackson Kreiter, CEO of newly announced Hier Design Inc. - a company committed to providing EDA tools that will "enable programmable devices to obsolete ASIC technology for most standard products." Kreiter is adamant that the emerging market for FPGA end-products has arrived - that Hier's phones are ringing off the hook with customers who need his tools to attack the challenges of FPGA design. Kreiter quotes liberally from Gartner Group data that shows a sharp drop in ASIC design starts over the last 3 years and a dramatic increase in PLD/FPGA design starts over that same period. He says we'll see less than 4000 ASIC design starts this year, compared to more than 400,000 FPGA design starts. It's tempting to ask Kreiter if he's comparing apples to oranges in quoting these numbers - if the ASIC design starts are bigger, more complex, higher performance end-products and some portion of those FPGA designs starts are slated for the prototyping boards. Kreiter is unfazed by the question and argues unequivocally that the "sweet spot in the ASIC market" is undergoing direct, head-on competition from the FPGA vendors. He says that 17% of the FPGA design starts today are at 500,000 gates and above, while FPGAs sized at 8 million gates with speeds of up to 400 MHz are not uncommon. Kreiter says those statistics should be compared with numbers that show 70% of the ASIC starts are in the 200 MHz range, with 2 million gates and below. The two markets are overlapping, Kreiter says, and the FPGAs are destined to win in the long run. Kreiter says, "I've talked with many people in the industry who are telling me that ASICs are simply going to die, that ASICs are in big trouble at 90-nanometer [process technologies] and below. Look at Xilinx. They've announced they're going to offer a million-gate FPGA for 25 bucks and I believe that's at 90 nanometers. I'm not saying that [the technology challenges] at 90 nanometers are a slam dunk as yet - we all admit it's not easy - but I do believe that FPGA working parts will emerge at 90 nanometers before ASICs do." Then there's the development cost/time issue, according to Kreiter. He says, "Let's say I've got a customer that wants a product and I decide to make the product on an FPGA. [Essentially], as soon as I program it, I can hand it right to the customer. However, if I do it on an ASIC, I've got to hand the design off to the manufacturing process and then wait months to get a working part. It can take up to half a year to get the product to the customer and, by that time, the customer's demands may have changed. Using an FPGA changes the time it takes between 'freezing' the design and getting it to the customer from many months for an ASIC to a couple of weeks for an FPGA. In fact, we believe that, on average, it takes at least 7 months longer to get an ASIC product to market compared to the time it takes to get a [comparable] FPGA product to market." Kreiter goes on: "Meanwhile, a lot of start-ups just can't afford to do an ASIC. Lucio Lanza [of Lanza Tech Ventures] tells me that we may reach a point [using next-generation process technology] where it's going to cost $40 million to $50 million to do an ASIC by the time you add in the engineering costs, mask costs, verification, and manufacturing expenses. You'll need to go after a $1.5 billion dollar market to defend those [levels of] development costs. That means a lot of people won't be able to penetrate that product market [if they go the ASIC route] because they'll need millions of customers to justify their initial costs." Kreiter does not pretend that the ASIC era is over: "It's true that ASICs are still going to be useful for high-volume production, because they're still cheaper [than an FPGA] when people are tying to milk a product for all it's worth. But, today, very few products get to that point - few products get to that level of market demand. And technology needs to be 'more' disposable, not 'less' disposable. Reprogrammable products are reusable. If an ASIC becomes obsolete - if it's no longer 'good' - you have to throw it away." Chuckling, Kreiter says, "I haven't heard of many people melting down an ASIC and reusing the materials. FPGAs, however, can be pulled out and reprogrammed. FPGAs are really the 'green' way to go." It's not surprising, according to Kreiter that large ASIC vendors are not enthused about pursuing FPGA-based market strategies. "It's like the large oil companies," he says. "Let's say I create a new car that works off a new fuel cell that can get 200 miles per gallon. Clearly, the oil companies won't be pushing that technology. Thank goodness we've got Xilinx and other FPGA vendors, who are strong, to push FPGA technology forward." Meanwhile, Brett Cline, Vice President of Marketing at Forte Design Systems, takes a more moderate stance when he says, "As a company, our technology is pretty independent of the ASIC-FPGA controversy. But I'm especially interested in the topic because I'm hearing our customers tell us that their design teams simply can't afford the $5 million to $10 million in design costs - engineering costs, mask costs, etc. - associated with an ASIC design. Currently, it take 9 to 12 months to build an ASIC and by the time you've finished with verification and tape-out, it can take up to 18 months. Just look at how long it takes to produce the RTL alone, and then verify it." "People have a couple of choices," Cline says. "Higher volume applications - there are not as many of those as there used to be - are still being built on ASICs for performance reasons and because some designs won't fit on an FPGA. But you have to see if the ASIC development costs are warranted in dollars earned per part sold. It's really a question of funding. The answer for smaller companies is [beginning to be] an FPGA rather than an ASIC. They [can bypass] the ASIC design team and string 3 or 4 FPGAs together, each at 1 or 2 million gates, and use the results for low volume products." Cline echoes Kreiter's sentiments regarding prospects for the ASIC market: "[Clearly], ASICs are going to continue to play a role for an extended period of time, but as FPGA devices are used to create more and more [products] with high gate counts, they'll prove to be a viable option because there's a quicker time to market and no need for [expensive verification and mask costs]. In large companies, they may continue to build things that are big enough and that demand enough performance that only an ASIC will do, but [for the small companies] the trade-offs may be starting to catch up." "Here at Forte, we need to understand the problems presented [in multiple markets]. An ASIC product has huge up-front costs. You have to build the RTL, buy the mask sets - which at 0.18 micron or 0.13 micron run from half a million to over a million dollars - and then go build the chip. Eventually you're into the project for $5 million to $10 million and you're not even in the market yet. Meanwhile, ASIC development costs have a 6-week delay built in between tape-out and mask sets. Say you've got 20 engineers on the project, what do you do with those 20 people during those 6 weeks?" "FPGAs are different, however. You can burn the code into the FPGA, run the system in a lab, and get the software development team involved a lot more easily, [which means] you can start bringing things to market a lot sooner." However, because many of the challenges in FPGA design have yet to be resolved, Cline says, "Clearly, if our customers didn't have time-to-market issues, they wouldn't be using FPGAs. But they are trying to get to market faster, and we're trying to address their needs from that standpoint." Still Cline says, the FPGA decision is not always an obvious one: "Some companies have been hesitant to deal with FPGAs. Some [had thought] that if they did their designs on an FPGA, they wouldn't need to do verification. They could just burn it and test it, but they found it [actually] took twice as long to do that as they had hoped. Meanwhile, I agree with Bob Payne. The platform argument is a viable one. There are many large, established vendors taking the same approach [as Philips], and I believe that platform-based design will continue to meet the needs of many." Cline says the market today is very fluid: "At Forte, we're trying to figure out a way to give all of those customers a way to shorten their time to RTL, FPGA vendors, ASIC vendors, platform vendors. We see them all striving to meet the same goals for their customers. Each of their customers is asking - 'What are my costs? What are my product specifications and requirements? What is my schedule deadline?'" "Then the [designers] have to pick out the best set of EDA tools, silicon providers, and software providers [to meet their customers' needs]. We want to be a significant part of our customers' design flows, whether it's an ASIC or an FPGA, and we find ourselves trying to meet both sets of needs - those of the ASIC vendors and those of the FPGA vendors. Since we focus on behavioral synthesis, we believe we allow people to cut time to RTL by 50-to-80 percent, regardless of whether they're addressing their design through an FPGA or an ASIC. Either way, it's about 6 months to RTL." Cline concludes, "I actually think that in the long run ASICs will go away, and I think people are taking a good hard look at whether or not they go to FPGAs [for their products]. As [economic] times become tight, however, they need to take that good hard look before they commit. Meanwhile, the problem at this point is almost technology independent. As long as people have the right mentality, if they [maintain] a sophisticated idea of the design process, their chance for success is high." Possible conclusions from all of this? The ASIC market is going to continue to be here for quite a while. The FPGA market is going to continue to grow. If you're a big ASIC vendor, don't lose sleep over it. If you're an FPGA vendor, keep all of your channels of communication open. If you're a small fabless start-up, give the FPGA option a good long look. If you're a large EDA vendor, hedge your bets. If you're a small EDA vendor, all bets are off. Industry News - Tools & IP Agilent Technologies Inc. announced Automatic Verification Modeling (AVM), a new simulation technology available in the Agilent Advanced Design System (ADS) 2003A. The company says the new technology allows for "design verification of communication circuits and systems at speeds up to 1,000 times faster than previous methods." Applied Wave Research, Inc. announced the Microwave Office 2003 simulation, layout, and EM analysis suite that focuses on RF design closure. The company says the enhanced suite provides monolithic microwave integrated circuit (MMIC), RF, and microwave engineers with an improved harmonic balance simulator, new time-domain simulation engines, an EM socket interface, and improvements in usability and performance aimed at wireless and high-speed wired applications. Camstar has introduced InSite Semiconductor TAP Edition, an application the company describes as "the first enterprise MES (manufacturing executing system) solution specifically designed for global semiconductor TAP (Test, Assembly and Packaging) manufacturing." The system is designed for use in single and multi-site production environments, and aims to provide support and lower implementation costs for semiconductor manufacturers, and to address consistent product quality across production sites. Using InSite, manufacturers can implement one-time order or specification changes without disrupting operations, and make the new information immediately available to all users. Get2Chip, Inc. introduced an enhanced version of its G2C-RC 02 RTL synthesis compiler for high-capacity, high-speed designs larger than 1 million gates. The company says G2C-RC 03 provides a complete RTL-to-netlist flow including datapath, timing and test optimization, and improves timing closure with 2x-capacity and 4x-runtime improvements over the previous version. The new product also includes Verilog 2001 support and open database access for chip finishing and customization with the standard interface. The company benchmarked G2C-RC 03 against G2C-RC 02 and tested it on customer designs. The results indicated a 37% post layout improvement in area on a 500,000-gate block while maintaining timing. G2C-RC 03 also produced post layout delay improvements of 18% on an 800,000-gate block and 61% on a "timing-critical" 2 million-gate block while maintaining area. Hier Design Inc. has named Innotech Corp. of Kanagawa, Japan, as its exclusive Japanese distributor. Innotech is also an investor in Hier Design. Interra Systems, Inc. announced support for the Verilog-2001 (IEEE-1364-2001) standard for Cheetah, the company's Verilog analyzer and high-end Verilog front-end for EDA products. It parses the complete Verilog language and creates an in-memory object model. Applications can then access design information instantly through an API. A new test suite is also being introduced, Beacon-2k1, which validates language compliance and includes over 4,500 test-cases for validating syntax, simulation semantics, and synthesizability subset based on the Verilog-2001 standard. Beacon is a family of test suites, which allows EDA tool developers to characterize tools across various language constructs and styles. LogicVision, Inc. announced that it has qualified the Prover eCheck equivalence checker for use in the LogicVision design flow. Prover Technology completed a series of test cases to validate interoperability with LogicVision's embedded test hardware. The companies say that the "combined solution enables at-speed test of multi-million gate SoCs, allowing customers to accelerate verification, reduce total development time and meet quality requirements." Magma Design Automation Inc. announced that the company offered product demonstrations at the China International Semiconductor and Integrated Circuit Exhibition & Seminar on March 24-26 in Shanghai, China. Mentor Graphics Corp. and Semiconductor Manufacturing International Corp. (SMIC) jointly announced that SMIC has chosen the Mentor Graphics tools, including Calibre, IC Station, and Eldo, as one of their internal production standards. James Sung, Vice President of Marketing and Sales for SMIC said, "We [have] aligned our physical verification flow with semiconductor companies which have standardized on Calibre. Meanwhile, Mentor has excellent custom design and simulation technology, and we have therefore chosen IC Station and Eldo for use in our internal development teams." Nassda Corp. announced version 3.0 of its HSIM, LEXSIM and CRITIC products. The new releases include integration with digital simulation and Verilog-A language support. HSIM v3.0 supports integration with Cadence Design System's NC-Sim digital simulator for enhanced full-chip verification, and supports both top-down and bottom-up verification flows - either digital or circuit-level representation can be selected as the top-level view for the design. Verilog testbenches can also be run directly with HSIM without a separate digital simulation and translation. LEXSIM v3.0 extends post-layout analysis by accepting all industry standard parasitic formats for integration into designers existing physical verification and extraction flows. Additionally, parasitic reduction for large global signal networks has been added in the new release for designs such as memories, where bit-lines and word-lines connect a large number of components. Pittsburgh Simulation Corp. announced that it has selected Dundee, Scotland as the location of its European headquarters. Earlier this month PSC announced plans to open a System Center in Europe with full application engineering support. Synopsys, Inc. and Semiconductor Manufacturing International Corp. (SMIC) jointly announced that SMIC has selected Synopsys' Hercules as one of its tools for layout verification and sign-off of its latest process technologies. Customers can also use Hercules during the design cycle, since the same tool is being used at SMIC for final production sign-off. James Sung, Vice President of Marketing and Sales at SMIC, said: "We must be able to deliver a cost-effective solution, quickly, to meet [customers'] product delivery windows. We trust Hercules' comprehensive feature-set and performance to quickly achieve sign-off for our latest process technologies." Also from Synopsys - Synopsys and the Chinese Academy of Sciences (CAS) announced they have signed an agreement to build an advanced SoC laboratory in Beijing. Synopsys and CAS say the lab will be the first facility of its kind offered by CAS and an EDA provider in mainland China. The lab will use Synopsys' design implementation and verification tools as design and education resources to develop ICs at 0.13 micron. Training and use of the SoC lab will be offered to researchers and graduate students at the 10+ institutes that CAS supports. After the technical lab is established, Synopsys and CAS plan to discuss future cooperation on joint development with respect to 0.09-micron IC design technology and flow. Under the agreement, Synopsys will provide CAS with complete design solutions and services, including an IP library and front- and back-end tools within Synopsys' Verification Platform and Galaxy Design Platform. Synopsys will also provide the laboratory with technical support and training services. CAS says it will standardize its next-generation deep-submicron "golden flow" on Synopsys tools. The newly established EDA Center of CAS will be responsible for the implementation of the collaborative plan. (Editor's Note: The following news item was incorrectly attributed to the wrong company in last week's newsletter. The item is being listed here again - this time correctly - along with apologies to Synplicity and Lightspeed Semiconductor.) Synplicity and Lightspeed Semiconductor announced that the two companies have signed a joint technology development agreement to provide support for Lightspeed's 0.13-micron Luminance family of Modular Array ASIC devices. Under the terms of the agreement, Synplicity will develop custom synthesis mapping technology for its Synplify ASIC software, optimized to Lightspeed's Luminance devices. Lightspeed will distribute Synplicity's Synplify ASIC .sel library and accept Synplify ASIC netlists and timing analysis results as input to Lightspeed's back-end place-and-route tools. Virage Logic Corp. announced that its product family is available for the Synopsys Galaxy Design Platform. The companies say that with Virage Logic's products working in Synopsys' design implementation product environment, large common customer bases will be able to reduce design production costs without having to change their existing design flow. Kevin Kranen, Director of Strategic Programs at Synopsys, said, "Synopsys has worked together with Virage Logic to develop high-quality views and support for Galaxy Design Platform. Our joint customers will benefit from this collaboration in the form of a smoother, more convergent implementation flow from RTL to production leveragin Virage Logic's silicon-proven IP." WaferYield Inc. introduced a new product, WAMA Mask, to reduce the cost of lithography masks for semiconductor processes. WAMA Mask prints several mask layers on a single reticle array, rather than using just one mask per layer. The company says this approach allows semiconductor manufacturers to achieve savings, as the cost of mask sets for deep-submicron fabrication goes above $1 million. WAMA Mask was designed to be scalable and customizable for steppers from ASML, Nikon, Canon and Ultratech, and most advanced process geometries. Implementing WAMA software does not require any changes in the manufacturing process - it collects and integrates input data from the existing environment for a multi-dimensional statistical yield analysis. The tool then generates an optimized wafer map for the stepper to help the reticle array design avoid manufacturing process problems. The company quotes Jerry Worchel, Senior Analyst at In-Stat/MDR., who said, "Design for manufacturability has become a main focus for the semiconductor and EDA industries as the ramp-up to 90-nanometer chips turned [out] to be extremely challenging, with yield issues being the bottle neck. In fact, yield problems at the 0.13-micron node still exist, and WaferYield's approach might go a long way in helping cope with some of the issues. Before addressing the 90-nanometer node, major yield issues at 130-nanometers must be resolved. Clearly, the market will benefit greatly from a solution that could bridge between design and manufacturing, helping to solve yield and design issues. WaferYiel addresses this domain with their WAMA products, which have long term growth potential by expanding from the manufacturing and test segments into the chip design domain." Xilinx announced the latest version of the company's free, downloadable programmable logic development system - the Integrated Software Environment WebPACK software. The design tool includes what the company says are several new "productivity and ease-of-use improvements," including an enhanced HTML Fitter Report for faster report generation, native language support for equation display for VHDL, Verilog, and ABEL, and updated versions of several tools including ModelSim-II Xilinx Edition. Industry News - Devices ARM announced that Conexant Systems, Inc. has licensed the ARM926EJ-S embedded processor core for use in its recently launched family of high-performance home network processors. Altera Corp. announced the availability of the Nios Development Kit, Cyclone Edition, a development and prototyping platform for a range of embedded applications. The company says the development kit provides everything designers need for system-on-a-programmable-chip (SOPC) development using the industry's lowest-cost FPGA family. The new kit includes version 3.0 of the Nios embedded processor, the Cyclone EP1C20 device, Quartus II design software, SOPC Builder system design tool, and a complete suite of software development tools. Also from Altera - The company, along with MJL Technology, Ltd., announced the immediate availability of the MJL Cyclone Development Kit, which is described as the first in a series of development kits based on Altera's Cyclone FPGA family. The MJL Cyclone Development Kit provides designers with a platform for designing, prototyping, and debugging high-volume systems using the Cyclone device family. Like the MJL Stratix Development Kit released in December 2002, the new Cyclone Development Kit includes a development board, Quartus II Web Edition design software, and several system reference designs. Altera says that "with up to four times the density of previous low-cost FPGA families and volume prices at less than $1.50 per 1,000 logic elements (LEs), Cyclone FPGAs are the optimal solution for high-volume, price-sensitive applications that previously required the use of fixed solutions such as gate arrays and standard cells, and are built on TSMC's all-copper, 0.13-micron process technology." Atmel Corp. announced the release of its AT73C202 Power and Battery Management standard product for cellular phones and wireless platforms. The AT73C202 is manufactured on Atmel's CMOS process, and according to the company includes all functions needed for a GSM phone to operate with power efficiency from a Lithium Polymer or Lithium-Ion battery, which the company says preserves its lifetime and autonomy. The AT73C202 has a low-voltage 1.8V/300mA high-efficiency DC-to-DC converter, a set of 7X low drop out voltage regulators, a battery charger, a 2.8V/1.8V SIM level shifter interface, a backup battery charger-regulator and circuitry which enables the DC-to-DC converter soft start, reset generation, power supply sequencing, temperature and voltage supervision. First Silicon Solutions (FS2) announced the In-Target System Analyzer for the Altera Nios 3.0 embedded processor. The FS2 System Analyzer includes a JTAG connection containing OCI (On-chip Instrumentation) core technology developed by FS2. The System Analyzer allows Nios software developers to debug real-time code and provides a single target connection for downloading, running and debugging software. The FS2 System Analyzer also enables communication between the host PC development system and the OCI core in the Nios embedded processor. Embedded developers can configure the OCI core using the Nios processor Megawizard to enable features such as on- and off-chip trace, even triggering and real-time trace collection. An entry level version of the debug tool is included in the recently announced Nios Development Kit, Stratix Edition, and Nios Development Kit, Cyclone Edition. Infineon Technologies AG announced the availability of a VCSEL (Vertical Cavity Surface Emitting Laser) diode with a 1310-nm wavelength, the first such diode to be produced by a supplier that can manufacture it in high volumes. The company recently demonstrated the new VCSEL diode operating in an intelligent small-form-factor-pluggable (iSFP) transceiver module. The two offerings enable manufacturers of optical devices, such as transceivers and transponders, to design what the company says are cost-saving solutions for data communications and telecommunications applications. Unlike the commonly used DFB (distributed feedback) and FP (Fabry-Perot) laser diodes, which emit light from the edge, VCSELs emit light from the surface. Intel Corporation announced three new processors for PDAs. The company says the new processors incorporate the latest microprocessor packaging and stacking techniques, and deliver higher performance and longer battery life in less space than previous versions. The company says PDA capabilities have increased significantly over the last year to include integrated 802.11 high-speed wireless Internet access, color screens, integrated cameras, and more. This has resulted in the need for greater processing and memory capabilities, all delivered by smaller chips. The new announcement includes two additions to the smaller, Intel PXA26x family, including the Intel PXA263 processor, Intel's first stacked processor for PDAs and the Intel PXA260 processor, a "pin compatible" product that the company says makes upgrading a PDA design easy for OEMs. The third product, the Intel PXA255 processor, is a replacement to the Intel PXA250 processor. LSI Logic Corp. announced production capability for "advanced flip chip packaging products" with the company's Gflx 0.11-micron copper and low k-based SoC product line. The company says designers can take advantage of "true low k and copper" in conjunction with advanced flip chip packaging and work towards design for next-generation communications, consumer, and storage applications. This announcement follows LSI Logic's Pad on I/O technology announcement, which places bond pads directly on top of active I/O circuits in a chip design, and is currently in production using copper/low k processes. Micron Technology, Inc. has introduced several new high-density 512Mb DDR400 components and has demonstrated them in a PC3200 platform. The 512Mb DDR400 devices are produced on 0.11-micron process technology and are compliant with the industry-standard JEDEC DDR400 specification. National Semiconductor Corp. announced what the company says is "the world's first family of integrated circuits that combine PLL and VCO functions in a single chip optimized for CDMA mobile handsets." By integrating the phase locked loop (PLL) and voltage controlled oscillator (VCO) functions into a single frequency synthesizer circuit, National says its designs reduce the required board space by 67 % when compared to designs that use discrete PLL and VCO circuits. PLDApplications announced the immediate availability of the Altera Stratix-based PCI-X SYS development board. The PCI-X SYS development board can be mounted with several Stratix devices in different sizes from 10,570 to 32,470 LEs. The board has two fully independent banks of 4Mx32-bit words of DDR SDRAM, runs on the PCI-X bus, and leans on the PLDA 64-bit 133MHz PCI-X IP core. The company says the new board "provides a rapid and high-bandwidth prototyping platform to FPGA or ASIC designers. It can also be used by customers at system-level in applications including DSPs, test & measurement, or data acquisition in various fields like components manufacturing, physical sciences, aerospace, and military." Qiagen N.V. and Agilent Technologies Inc. have agreed to co-market lab-on-a-chip products for molecular biology to the life science markets under a non-exclusive agreement. Qiagen said the companies will co-market the Agilent 2100 bioanalyzer and LabChip kits with Qiagen's consumables and instruments for the separation, purification and handling of nucleic acids and proteins. The combined products are intended to allow molecular biologists and biochemists to obtain reliable results in the analysis of biomolecules such as DNA, RNA, proteins and cells. Xilinx, Inc. announced it is shipping all advanced FPGA product lines on 300mm wafers including the Virtex-E, Virtex-II, Virtex-II Pro, and Spartan-IIE FPGAs. The company says it is among the highest volume purchasers of 300mm wafers in the world, and employs a dual fab strategy whereby products are designed to work on a variety of processes. By partnering with both IBM and UMC, Xilinx says it can maintain parallel development on "leading-edge" process technology from IBM and low cost process technology available today on 300mm through UMC. Wim Roelandts, President and CEO at Xilinx, said, "Our move to 300mm is an essential element of our strategy to rapidly drive down costs for our customers to further narrow the ASIC gap." Coming soon to a theater near you Verisity Ltd. announced a new training course called Specman Elite Advanced Training. The company says the course teaches verification methodologies that focus on a coverage-driven verification (CDV) methodology, which in turn provides engineers with a cookbook approach for applying the methodology. The company adds that verification engineers working with a CDV methodology have been successful at achieving first-pass silicon success, that CDV is becoming an important component of mainstream verification environments. The strategy includes verification reuse where verification environments can be reused, and verification environments created at the module level can be brought up to the chip and system level. Verisity says both of these types of verification reuse techniques can provide productivity gains for verification teams, if done correctly. ( www.verisity.com ) Newsmakers Integre Technologies - A new electronic design services company has opened its doors. Managing Partners, Mark Blejwas and Fred Rakvica, announced that the company - based in Rochester, NY - was formed to offer digital and analog design services to electronic design customers in North America. The company says its design services team includes individuals experienced in both verifying and designing silicon circuits and systems with up to 5 million gates, including designs which incorporate both mixed signal and digital components for wireless, embedded, and RF applications. Blejwas and Rakvica say the company's consultants have "decades of experience" and will focus on assisting customers with needs in both the ASIC and FPGA flows. Rakvica said, "We saw the downturn in the economy as an opportunity to start an electronic design services company. We are growing our company now, and preparing to take advantage of the upturn." Blejwas added, "The marketplace has forced efficiency in the ASIC flow. In the long run we see this as a plus for our business. [Additionally], the typical separation of digital and analog efforts is disappearing. Our expertise in both digital and analog flows allows us to assist customers in this transition." Rakvica has 20+ years' experience in design, including ASICs, FPGAs, PCBs, and embedded software. He has a BSEE degree from Clarkson University and an MSEE from the Rochester Institute of Technology. Blejwas has experience across both ASIC and FPGA flows, including PCB design, embedded software, test fixtures, and manufacturing support. He has a BSEE degree from Lafayette College and an MS from Rensselaer Polytechnic Institute. Blejwas is a licensed P.E. in the state of New York. In the category of ... Point - Counter Point In his March 21st newsletter, American Technology Research's Erach Desai presented his perspective on the impact of industry standards bodies on competition and forward progress in technology. His viewpoint offers an interesting counter point to the position laid out here in the March 3rd issue of EDA Weekly . With Desai's permission, here are some excerpts from his March 21st newsletter: "Standard setting committees are made up of some of the smartest people in the industry, whose goal is to attack some very difficult technical problems and develop a consensus-driven standard while still pushing the leading edge. However, [I] disagree with many of the op-ed pieces in the technology press, from editors whom I respect, extolling their virtues." "Specifically, I disagree on the role of standards bodies from a franchise-building economic-value perspective." "Intel and Microsoft would not be the franchises they are today if the x-86 and Windows de facto standards had been determined by committee. What standards committees did achieve after market forces had taken their course was to ensure that the infrastructure around the Wintel platform was based on standards that enabled easier proliferation of the platform. There are those who will argue that these are "one-off" exceptions in a lifetime, but I would argue that there are many smaller scale examples." "A somewhat similar analogy also played out in the electronics design world, albeit with a small-scale economic impact. It was in the arcane area of hardware description languages (HDLs) that raised the "level of abstraction" of specifying electronic designs from "gate level" to "register transfer" level (RTL). Translated in human-speak: rather than communicate with symbols (or sign-language), engineers found it more efficient to communicate in an English-like language, which captured the essence of the design functions. In short, somewhat chronological order, the story unfolded as follows (our simplified notion of history)." - An East-coast company named Gateway developed a proprietary language called Verilog and a simulation environment that was optimized around this language. - Standard bodies popped up, over time, as it became obvious that HDLs would be the way to go. The one with the most critical mass was VHDL, which seemed to get some mil/aero endorsement and traction in Europe. - Cadence Design bought Gateway, and turned the Verilog language into a de facto standard through their extensive sales channel. After a few years, partly by being nudged and party being self-serving, Cadence "donated" the Verilog language into a standards body. - A few years later, Synopsys capitulated on their efforts to hammer home VHDL as the industry standard by purchasing Viewlogic (which had purchased a Verilog simulator clone company called Chronologic). "The point of this story (and some will again argue that it was an exception) is that market forces enabled Verilog, a proprietary language, to become the de facto standard which was then improved upon through a unified standards body process. Cadence enjoyed the early benefits of being the first-to-commercial-use provider of Verilog-based verification tools, and everyone lived happily every after." --Peggy Aycinena is a Contributing Editor and can be reached at peggy@ibsystems.com . You are subscribed as: [dolinsky@gsu.by]. Cafe News is a service for EDA professionals. EDAToolsCafe respects your online time and Internet privacy. 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